that shit is weird at night
the regrowth plants, for years
Posted by renesis at 14:11 | permalink | 0 comments
lordpil's blog
rhettlap: yes, hot
there was no clouds or smoke today
was oddly normal
dunno work is going fine for me
one day i will write a book or rant for 20min about it
so is the fire out yet or what?
i figure they are just hiking around in the mud spraying dirt with water
oh
hi
how fucked up is that, TODAY WE HAVE TO LOOK FOR TINY BABY FIRES IN ALL OF ANGELES NATIONAL FOREST
like how many weeks before they say okay fuckit its out
Posted by renesis at 14:06 | permalink | 0 comments
with a sharpie so i just fixes it with iso alc
haha
Posted by renesis at 11:59 | permalink | 0 comments
hmm
im not sure you can with the data they give you
like you have to know how fast the heat will spread
which involves the material and its exposure to ambient vs its volume
but thats pretty much why they have SOA and peak/sustained current data
safe operating area
like how much current it can handle at what voltages
and then there will be a line which indicates the current it can handle before the bonding wire just vaporizes
kevtris: i did that once =\
Posted by renesis at 11:54 | permalink | 0 comments
simulating load
like 15A might be fine for the fet but maybe burning 15A*6V for 2mS isnt
or maybe 15A is just too much, so try and reduce that and just make sure the power youre dissipating isnt getting the fet to some ridiculous temp
c/w is how many C the device will rise dissipating that much current
thermal resisance to ambient is how hot itll get in free air
thermal resistance to ambient is how hot itll get attached to an ideal heatsink (0C/W)
yeah, basically steady state because of heat transistion times
but like, just because its not hot on the outside doesnt mean the heat doesnt exists\
its just inside on the die
Posted by renesis at 11:49 | permalink | 0 comments
kinda but its gcc stuff to it just kinda means photo-editify to me when i read it
=\
and like they dont really says what is doone in file comments so im just confuzed
fooozed
fuck im tired i wanna go to sleep
*so it
thats cool ive seen the video show at the tool concert
hmm
check the datasheet for c/w and consider your heatsink or lack of it and make sure your peak current and duration isd within the transistors peak max
Posted by renesis at 11:43 | permalink | 0 comments
itll just take a long, long time for your caps to fill up
i would try like 10us, 100us, 1ms, 10ms, 100ms, see what average and peak power look like
like, if you fill the caps at 1.5A, it maybe takes 24ms to charge up instead of 2.4ms
whats c,v
tldr
Posted by renesis at 11:37 | permalink | 0 comments
because pulling tons of current isnt the problem so much
pulling any current while its in transistion can be
like the 15A part of the current plot prob isnt where its burning power
its prob around where its doing 7A during the rising current section of the plot
the more turnon time you have, the longer it will take to fill the caps, too
so like youre maybe burning less peak power, but the average power might be greater
like, if you make the turnon time way more than the 15A cap fill time, you maybe effectively limit the current and power
Posted by renesis at 11:32 | permalink | 0 comments
yeah the plot has labels
current is labeled by part
yeah you dont
with nodes unless you label them
or just remember them
hey do you know how to plot power?
do you know how to get voltage across a part?
like reference a non gnd node
okay or that
Posted by renesis at 11:27 | permalink | 0 comments
dunno really
it depends on the capacitive load
simulate it
sure
but yeah if you can get or make a decent model for your pmos, try and sim the turnon event to see what the current spikes look like
hackers, obviously
and its because your desktop is a compilation of more than one desktop directory
like, itll be you user + all users, or something
*your
like how your start menu shit lives in two or three diff docs and settings folders
(i fucking hate that shit)
Posted by renesis at 11:21 | permalink | 0 comments
you prob want a resistor in series with your pulldown circuit
the pullup is keeping it off, so itll control your turnoff time
you have to deal with the resistors creating a divider, tho
alternative you use a high side switch, and have a resistive pulldown
like you use an npn to switch a pnp on the fet gate
but now you have race issues during control circuit turnon
if your control circuit is powered by the voltage it is switching
Posted by renesis at 11:16 | permalink | 0 comments
if youre driving the SMPS itll prob handle overcurrent stuff, check the gate capacitance on the fets you want to use and try and tune the pullup resistor with that so you get decent turnoff time
sounds like the smps will be disabled when youre switching anyway
yeah its usually specified gate to source
yeah for stuff like that you dont really want the fets to be working linear
your application, its not really constant duty
so you just have to make sure it can survive the transition, you prob dont have to worry about thermal breakdown over time
yeah but this is after the caps, no?
yeah for this type of stuff the rise time might help
if the pmos before or after the supply capacitors for the smps
Posted by renesis at 11:11 | permalink | 0 comments
anyway the smps prob has overcurrent protection
and the fet can maybe deal with a capacitive load for short duration
like, basically you are dumping the smps output cap so if theyre not super huge might not even be enough energy to burn the fet
oh
Posted by renesis at 11:06 | permalink | 0 comments
never design for normal circumstance
design for when shit is fucked up
anyway, 10A*6V is 60W
assume the load is resistive and its still 30W
ohms laws fool
half the voltage is half the current
thats a bit scarier
and if its for a capacitive load, turnon current can be like hundreds of watts
calculated, from the datasheet, or measured?
we measured in supply in school it was doing like 96% with a light load
i was pretty fuckin impressed, heheh
Posted by renesis at 11:00 | permalink | 0 comments
draw it
if youre depending on the pullup to switch the gate, you better be doing long durection stead states between your switching
it forms an RC with gate capacitance, so for rapid switching its totally fail
switch for what
at what current
if its for heavy current its likely to burn your fet during transistions
its transistion time
because youre dropping volts *while* pulling current
fets in a switching application should be doing one or the other
not both
how many voltage
and what type of load
heh @ HOW MANY VOLTAGE
Posted by renesis at 10:55 | permalink | 0 comments
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