maybe on the mains side, dunno wtf that power entry connector is
its their top performer
i wonder in what
it says 'NO: Cable drawing attention to itself'
i dunno man, thats not exactly inconspicuous
Posted by renesis at 04:32 | permalink | 0 comments
jitter thing was also a bit of an issue on another project, i think using AD chips, they ended up using a sample rate converter just to clean up the PLL
doesnt seem to be an issue until you start trying to sync multiple things
so yeah in this case, maybe not even a problem
they might mean the bit clock rate, which is something like 15MHz? for 192khz, stereo 24bit, and protocol overhead
those are some sexy power cables
they prob cost that more than that much to make, the fabric cable cant be cheap
and they prob had to tool up for the wall connector
Posted by renesis at 04:26 | permalink | 0 comments
ha @ future functionality
'we werent done but boss says we has to ship it'
hopefully they mean at a multiple of the audio sampling rate
teknique: supposedly PLL clock jitter on a lot of the arm chips is pretty shitty compared to audio clock generators and sample rate converters
coworker types went to ST about the problem in STM32 stuff, and theyre like NO CHECK OUR DATASHEET and coworkers told them what they were doing and how they were testing and ST's response was 'OH FUCK'
well you can use the sony ones with enhanced shielding
Posted by renesis at 04:20 | permalink | 0 comments
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